400Mbps/ch SiDP Receiver for Mobile TFT-LCD Driver IC  移動TFT-LCD驅動IC客戶端接收的信號速度是 400 Mbps

Abstract摘要

A high speed serial interface receiver is realized in a 0.18um highvoltage CMOS technology for a mobile 24-bit hVGA TFT-LCDdriver (LDI) IC. 在0.18微米的高壓CMOS技術下，移動的24位HVGA TFT-LCD驅動器（LSI）IC可以實現一個高速串行接口接收器的設置。The type of serial interface implemented is calledSimple Display Port (SiDP) and is intended to replace the legacyRGB interface in the LDI IC’s. The receiver consists of one clockand two data channels, and thereby reduces the number of signallines going through the hinge of a mobile phone from 28 down to6. All channels conform to Sub Low-Voltage DifferentialSignaling (SubLVDS) convention. The total transfer rate can beup to 800Mbps for two data channel. The current consumptionwas 5.4mA at the data rate of 600Mbps.上面的數據傳輸速率為600 Mbps，電流消耗是5.4毫安。

Introduction 介紹

As the display resolutions and color depths of the LCDs in mobileapplications increase, higher data rate and more number of datalines are required in the interface between a display driver IC andmodem or application processor (AP). Higher data rate causeselectro-magnetic interference (EMI) problem and many data lineslead to poor reliability due to interconnection cable fatigue nearthe hinges of clamshell-type mobile phones. Recently, manyapproaches to these problems have focused on the high speedserial interface such as Mobile Display Digital Interface (MDDI)and Mobile Industry Processor Interface (MIPI) [1, 2].This paper describes a high speed serial interface receiver formobile display driver ICs to satisfy requirements of low pin count,low power consumption, and high data throughput.本文介紹了一種高速串行接口下的移動接收器顯示的驅動IC，以滿足低驅動參數，低功耗和高數據吞吐量的要求。

 

SiDP ArchitectureSIDP架構

Figure 1 shows a system block diagram of SiDP. 圖1示出了一個SIDP系統框圖，A transmitter inan AP serializes the RGB parallel CMOS signals into SubLVDSsignals and generates a clock signal with the pixel clock frequencyusing a PLL. The interconnection layer consists of one clockchannel and two data channels. The number of data channels canbe programmable depending on the bandwidth needed. The SiDPreceivers in 1-channel mode and 2-channel mode support a screenresolution of QVGA and VGA including hVGA, respectively.This receiver in a LCD driver IC deserializes serial SubLVDSsignals into RGB parallel CMOS signals. The internal DLLrecovers high speed data synchronization signal from the clock.At full speed, each data channel transfers at 400Mbps, whichtranslates to the maximum total transfer rate of 800Mbps for twodata channels.  http://ukthesis.org/jsjwl/#p#分頁標題#e#

Fig. 2 shows the data format for two data channel mode with a 24-bit color depth. 圖2顯示了兩個數據通道模式，24位色彩深度的數據格式。The number of bits on each channel for one clockperiod is fifteen. The 24 RGB data are separately transferred ontwo channels. “VS” and “HS” are vertical and horizontalsynchronization bits, respectively. “RES” is the reserved bit forthe future use and its default state is logic low. “CP” is the parity

bit of data payload and is high when the number of bits which arelogic high is even. 數據有效的加載了荷量和高度，甚至邏輯數據下的數據顯示。Therefore the number of high bits is odd whenthere is no error. If parity error is detected, the receiver outputs theprevious error-free pixel information instead of the invalid pixelinformation. This error correction scheme makes it difficult todetect image errors by human eyes since two adjacent pixels oftenhave same value in a display screen.

By transferring CLK signal at the pixel clock frequency, pixelsynchronization information is sent to the receiver without anyadditional synchronization bits.通過傳送CLK信號的像素傳送的頻率，沒有任何額外的同步比的影響下，像素可以將同步信息發送到接收器。 This CLK signal is safelytransmitted to the receiver due to low clock frequency comparedto the data channel frequency. Also it shows better EMIcharacteristics compared to high clock frequency.

The number of signal lines going through the hinge is reducedfrom 28 down to 6. It improves the reliability of interconnectioncable in mobile phones and simplifies the design of flexibleprinted circuit board (FPC). A SubLVDS signal shows better EMIcharacteristics than that of CMOS signal because of the smallvoltage swing and differential signaling characteristics. Thisreceiver enables cutting down the total system power consumptionas the data throughput is especially increased since the channelcurrent is little depending on the data rate compared to the legacyparallel interface.

By incorporating the high speed serial interface, SiDP, intomobile TFT-LCD driver, an additional receiver chip is notrequired.通過納入到移動的TFT-LCD驅動器的高速串行接口，SIDP，一個額外的接收器芯片，并不是必需的。