Figure 5. The waveform of an input signal of transmitter and output signal of receiver.
圖5發射機和接收機的輸出信號的輸入信號的波形圖
Fig. 5 shows the waveform of signals at the output node of the pattern generator (input signal of transmitter) and the input node of the LCD module (output signal of receiver) at the pixel clock frequency of 20MHz, which means that serialized data rate is 300Mbps/ch. The signal at the top, a RGB signal, is applied to the transmitter chip and the signal at the bottom is recovered from the receiver with a propagation delay of 264ns which is gate delay in the transmitter and receiver.
圖5示出了在圖案產生器（發射器）的輸入信號的輸出節點的信號的波形的LCD模塊（接收器）輸出信號的輸入節點，在像素時鐘頻率為20MHz，表示序列化的數據速率是300Mbps的/ ch的。在頂部，一個RGB信號#p#分頁標題#e#，該信號被施加到發射器芯片，并回收在底部的信號從接收器的傳播延遲是在發射器和接收器的門延遲264ns。

Figure 6. The image of the LCD module
圖6 液晶顯示模塊的形象
Fig. 6 shows the image of LCD module at the data rate of 300Mbps/ch. In the module test, the data transfer rate was tested up to 337Mbps/ch which is the maximum frequency for VGA application. In addition, the driver IC is also tested on wafer level and the maximum data rate of the receiver has been measured at 400Mbps/ch.
圖6示出在數據速率300Mbps/ch的圖像液晶顯示模塊。模塊的測試，測試的數據傳輸速率高達337Mbps/ch（VGA）系統的最大頻率。此外，在驅動器IC上測試晶圓級和最大數據傳輸速率#p#分頁標題#e#的接收器以400Mbps/ch測量的。
Table 1 summarizes the measured performance characteristics of the SiDP receiver. The minimum input differential voltage is 70mV and the common mode voltage range is from 0.6V to 1.2V. The number of data channel can be selected in 1 or 2 according to the display resolution and color depth. In case of two data channel mode, the current consumption is 5.4mA at the data rate of 300Mbps/ch. This data rate can support up to 24-bit VGA display. The input load termination resistor of 80~120Ÿ is internally implemented on a chip.
表1總結了SIDP接收器測得的性能特點。最小的輸入差分電壓為70mV的共模電壓范圍是從0.6V到1.2V。可以選擇在1或2的數據信道的數量，根據顯示器的分辨率和顏色深度。在兩個數據信道模式的情況下，電流消耗在數據速率300Mbps/ch#p#分頁標題#e#的5.4毫安。此數據速率最多可支持24位VGA顯示器。輸入負載端接電阻為80?120Y內部實現在一個芯片上。

Table 1. Characteristics for SiDP receiver
表1 SIDP接收特性
5. Conclusions
總結
The SiDP receiver is realized in a 0.18um high voltage CMOS technology for a mobile 24-bit hVGA TFT-LCD driver IC. The receiver adopts SubLVDS as a physical layer and supports 1 and 2 data channels depending on the bandwidth needed. The number of signal lines going through the hinge of a mobile phone is reduced from 28 down to 6. The maximum transfer rate is up to 800Mbps for two data channel. The current consumption is 5.4mA at the data rate of 600Mbps.
SIDP接收機在0.18微米高壓CMOS技術，通過移動24位HVGA TFT-LCD驅動IC來實現。接收機采用SubLVDS作為物理層，并支持1#p#分頁標題#e#和2的數據信道，根據所需要的帶寬。信號線的數目的移動電話的鉸鏈經歷從28減少到6。最大傳輸速率高達800Mbps的兩個數據通道。該電流消耗5.4毫安的600Mbps的數據速率。
6. Acknowledgements
致謝
The authors would like to thank Texas Instruments for the transmitter http://ukthesis.org/ygsslwdx/ chips and PCBs.
筆者感謝德州儀器發射機芯片和多氯聯苯。
7. References
參考資料
[1] Qualcomm, “Mobile Display Digital Interface Specification”, 2003.
[2] MIPI, “Draft MIPI alliance D-PHY specification”, 2005.
[3] Nokia, “Compact Display Specification”, 2005.